module clk8gen
		(clock, resetn, clk8);
input			clock, resetn;
output			clk8;

reg				clk8, clk4, clk2;

always @(posedge clock or negedge resetn)
begin
	if (~resetn) clk2 <= 0;
	else clk2 <= ~clk2;
end

always @(posedge clk2 or negedge resetn)
begin
	if (~resetn) clk4 <= 0;
	else clk4 <= ~clk4;
end

always @(posedge clk4 or negedge resetn)
begin
	if (~resetn) clk8 <= 0;
	else clk8 <= ~clk8;
end
endmodule
		